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CAD and Integration Engineer, Silicon

Meta· Engineering
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Hybrid (Sunnyvale, CA)$178k - $250kFull-timePosted 1mo ago

About the role

Lead CAD and integration engineer to shape methodology and physical implementation infrastructure for custom silicon programs, defining CAD flows from RTL/schematic to foundry-ready GDS, establishing best practices across synthesis, place-and-route, analog mixed-signal integration, and physical signoff, while building automation frameworks and integrating AI-assisted design tools to accelerate silicon velocity.

Responsibilities

  • Define and own end-to-end digital implementation methodology including RTL-to-GDS flows, synthesis, place-and-route, DFT insertion, and multi-corner physical signoff
  • Lead analog mixed-signal physical integration strategy, establishing constraint authoring, floorplanning guidelines, and interface protocols between custom and digital domains
  • Develop and maintain CAD automation infrastructure using Python, SKILL, and Tcl to reduce manual effort across implementation, tapeout, and regression workflows
  • Integrate AI and LLM-assisted coding tools into CAD methodology to improve design automation productivity across the silicon engineering organization
  • Drive physical signoff convergence across timing, power, noise, and design rule checks to produce foundry-ready deliverables on schedule
  • Establish 3D integration and heterogeneous packaging flows including die-to-die interface planning, cross-die timing closure, and bump/interposer constraint management
  • Partner with foundry contacts on PDK qualification, design rule interpretation, and process design kit updates for leading-edge technology nodes
  • Define low-power implementation methodology including multi-voltage domain integration, UPF-based power intent authoring, and power analysis signoff
  • Provide technical direction to other engineers on CAD methodology decisions, flow architecture, and implementation best practices across multiple concurrent tapeout programs
  • Communicate implementation status, methodology decisions, and risk assessments to circuit designers, layout engineers, and program leadership

Qualifications

  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 8+ years of industry experience in VLSI CAD, physical implementation, or silicon design methodology across multiple technology nodes and tapeouts
  • Expertise in full RTL-to-GDS digital implementation flows including synthesis, place-and-route, DFT, and multi-corner physical signoff using industry-standard EDA tools
  • Experience with analog mixed-signal physical integration including constraint authoring, floorplan coordination, and interface management between custom and digital design domains
  • Proficiency in scripting and automation using Python, SKILL, Tcl, or equivalent languages to build and maintain CAD flow infrastructure
  • Experience communicating methodology decisions, tapeout risk, and implementation status to cross-functional partners including circuit designers, layout engineers, and foundry contacts

Skills

Required:RTL-to-GDS digital implementationAnalog mixed-signal physical integrationScripting and automation (Python, SKILL, Tcl)
Nice to have:AI-assisted design tools / LLM-based coding
Last updated Oct 23, 2026. Interested? Apply on the company site.

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