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Substrate IC Package Layout Design Engineer

Etched· Architecture
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TaipeiFull-timePosted 4w ago

About the role

Role focused on end-to-end design of complex IC substrate packages for high-power, high-speed AI processors, including multi-layer substrates (>50mm), robust power delivery (>700W), and high-speed signaling (>50GHz) with CoWoS interposer integration. Collaborates with silicon, SI/PI, packaging, and OSAT teams to ensure manufacturability and performance.

Responsibilities

  • IC Substrate Layout Design
  • Lead the design and development of complex IC substrate layouts for high-power AI processors and accelerators.
  • Design large (>50mm) and complex multi-layer substrate packages with high pin counts and dense routing requirements.
  • Ensure robust power delivery designs capable of supporting >700W custom silicon solutions.
  • High-Speed Signal Routing & Integrity
  • Develop high-speed signal routing solutions capable of supporting >50GHz signaling while minimizing signal integrity issues such as loss and crosstalk.
  • Collaborate with SI/PI engineers to define signal integrity and power integrity requirements and implement solutions in substrate layout.
  • Advanced Packaging & CoWoS Integration
  • Optimize CoWoS (Chip-on-Wafer-on-Substrate) interposer designs for thermal and electrical performance.
  • Work closely with chip design, packaging, and manufacturing teams to ensure design feasibility and manufacturability.
  • Design Validation & Verification
  • Perform DRC (Design Rule Check) and LVS (Layout vs. Schematic) verification for all substrate designs.
  • Develop and maintain design documentation and guidelines for future substrate designs.
  • Support design reviews and provide technical guidance to junior team members.

Qualifications

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • 10+ years of experience in IC substrate layout design for high-performance processors or accelerators.
  • Extensive experience with large substrate packages (>50mm) and complex high-density layouts.
  • Proven experience with high-power (700W+) package designs and robust power delivery networks.
  • Expertise in high-speed signaling design (>50GHz) and mitigating signal integrity challenges (crosstalk, reflections, impedance mismatches).
  • Strong experience with CoWoS (Chip-on-Wafer-on-Substrate) interposer design and the impact of the substrate design to support CoWos.
  • Advanced proficiency in Allegro Package Designer (including constraint management, routing, and design verification).
  • Deep understanding of SI/PI principles and how they apply to package-level design.
  • Strong analytical skills and ability to work effectively in a fast-paced, cross-functional team environment.

Skills

Required:Allegro Package DesignerPower IntegritySignal Integrity

Benefits

  • Competitive compensation packages, including generous equity packages
  • Comprehensive insurance coverage and other top-of-market benefits
Last updated Sep 24, 2026. Interested? Apply on the company site.
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About Etched

Etched is building frontier inference clusters: co-designs chips, racks, software and manufacturing to push the pareto frontier for AI hardware.

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