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Silicon Packaging Engineer (SIPI)

Meta· Engineering
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Sunnyvale, CA$178k - $250kFull-timePosted 4w ago

About the role

Signal Integrity and Power Integrity (SI/PI) Engineer responsible for chip-package-system co-design for 2.5D/3D heterogeneous packaging in AI accelerator and HPC silicon, overseeing SI/PI requirements from architecture to post-silicon validation across interposers, 2.5D/3D stackups, and high-density substrates.

Responsibilities

  • Chip-Package-System Co-Design: Drive SI/PI requirements analysis and optimization into product definition — chip floorplan, bump map, power tree structure, and net topology — for HPC and AI silicon built on 2.5D/3D package technology.

Qualifications

  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 8+ years of experience with signal integrity analysis, simulation, and measurement
  • Proficient with HFSS, Sigrity, Hspice, and/or other simulation tools
  • Understanding of impedance control, transmission line and PDN characterization, feasibility studies and design guidelines
  • Experience with 2.5D/3D package design (silicon interposer, silicon bridge, 3D die stacking, STA, voltage budgets)
  • Expertise in signal and power integrity for high-speed interconnects (HBMx, D2D, Ethernet, PCIe, etc.)
  • Familiarity with post-Si test environment on memory (HBM/DDR4/LPDDR4/DDR5/LPDDR5) or high speed SERDES
  • Familiarity with next-gen memory and chiplet standards and timing budgets
  • Package-level SI/PI understanding across silicon, package, and board

Skills

Required:Chip-Floorplan optimization2.5D/3D packaging designHigh-speed interface design and analysisPDN/impedance analysisSimulation flowsPost-silicon validation
Nice to have:Collaboration across cross-functional teams

Benefits

  • Benefits information referenced in posting (see Meta benefits)
Last updated Oct 23, 2026. Interested? Apply on the company site.

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