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Design Verification Engineer, Silicon

Meta· Engineering
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Sunnyvale, CA$146k - $209kFull-timePosted 4w ago

About the role

Meta Reality Labs is building custom silicon for AR/VR devices. As a Design Verification Engineer on the silicon team, you will develop and execute verification strategies for digital logic blocks and subsystems to bring high-performance, low-power silicon from specification to tape-out.

Responsibilities

  • Develop and own verification plans for digital logic blocks and subsystems within custom AR/VR silicon, covering functional coverage, corner cases, and compliance requirements
  • Design and implement constrained-random UVM testbenches to verify complex RTL designs including processors, interconnects, memory controllers, and multimedia accelerators
  • Define and close functional coverage models and code coverage metrics to ensure thorough verification of design intent
  • Collaborate with RTL design engineers to review microarchitecture specifications and identify verification risks early in the design cycle
  • Develop and maintain simulation infrastructure, regression frameworks, and automated test suites to support continuous integration of design changes
  • Perform formal verification and property checking on critical design blocks to complement simulation-based verification
  • Debug failing simulations and regressions by analyzing waveforms, log files, and RTL code to root-cause design or testbench issues
  • Partner with post-silicon validation and firmware teams to develop pre-silicon test content that transitions to hardware bring-up
  • Contribute to verification methodology improvements, including reusable verification IP and shared infrastructure across the silicon team
  • Track and report verification progress, coverage closure status, and risk areas to design and program management stakeholders

Qualifications

  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 6+ years of experience in digital design verification, including development of UVM-based constrained-random testbenches for complex RTL blocks or subsystems
  • 6+ years of experience with hardware description and verification languages including SystemVerilog and/or VHDL
  • Experience defining and closing functional coverage models and code coverage metrics for complex digital designs
  • Experience debugging RTL simulations using waveform analysis tools and log-based root-cause analysis
  • Experience with scripting languages such as Python or Perl for test automation, regression management, or coverage analysis

Skills

Required:UVM-based constrained-random testbenchesSystemVerilog and/or VHDLFunctional coverage modelingDebug RTL simulationsPython or Perl scripting

Benefits

  • Benefits not listed in the excerpt; available per Meta benefits policy
Last updated Oct 23, 2026. Interested? Apply on the company site.

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