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Physical Design Engineer, Reality Labs Silicon

Meta· Hardware
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Sunnyvale, CA$146k - $209kFull-timePosted 4w ago

About the role

Meta seeks a Physical Design Engineer to translate RTL designs into optimized silicon implementations for VR/AR devices, leading floorplanning, placement, clock tree synthesis, routing, and signoff, in collaboration with architecture, design, and verification teams.

Responsibilities

  • Lead physical implementation of complex blocks and subsystems from floorplanning through tapeout, including placement, clock tree synthesis, routing, and physical verification
  • Define and drive physical design methodology, constraints, and flows to meet power, performance, and area targets for custom silicon in VR and AR products
  • Perform static timing analysis and timing closure across multiple process corners and operating conditions
  • Develop and optimize power delivery network strategies, including IR drop analysis and electromigration sign-off
  • Collaborate with RTL designers and architects to provide physical design feedback that influences microarchitecture and floorplan decisions
  • Partner with design verification and DFT teams to ensure physical implementation supports functional correctness and testability requirements
  • Drive physical verification sign-off including DRC, LVS, and antenna checks in advanced process nodes
  • Identify and resolve physical implementation bottlenecks related to congestion, timing, and power through iterative analysis and targeted optimization
  • Contribute to the development and continuous improvement of internal physical design flows, scripts, and automation to increase team efficiency

Qualifications

  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 6+ years of experience in physical design of complex digital ASICs or SoCs, including floorplanning, placement, CTS, routing, and sign-off
  • 6+ years of experience with static timing analysis and timing closure in advanced process nodes (7nm or below)
  • Experience with industry-standard physical design EDA tools such as Cadence Innovus, Synopsys ICC2, or equivalent
  • Experience with physical verification flows including DRC, LVS, and antenna sign-off
  • Experience with power analysis and power delivery network implementation, including IR drop and electromigration analysis

Skills

Required:Physical design flow ownershipStatic timing analysisPower integrity and PDN

Benefits

  • Benefits information available via Meta careers page
Last updated Oct 23, 2026. Interested? Apply on the company site.

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