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IC Layout Engineer – Optical Engine Silicon

Lumilens· Engineering
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SingaporeFull-timePosted 4w ago

About the role

Lumilens is hiring an IC Layout Engineer to own layout for electronic ICs (EICs) and photonic ICs (PICs) for AI data centers, working with a senior layout engineer and global design teams. The role focuses on parasitic-aware, high-speed analog/mixed-signal layout, integration of electronic and photonic dies, and contributing through tape-out and top-level assembly.

Responsibilities

  • Own layout for assigned analog and mixed-signal blocks: device placement, matching and symmetry, shielding, guard rings, and routing, from floorplan through to clean sign-off.
  • Execute parasitic-aware layout — build to the constraints given by designers, run extraction, and take the results back to them when the layout says something the schematic did not expect.
  • Route high-speed signal paths with attention to impedance, coupling, and return paths, and lay out passive and electromagnetic structures under senior direction.
  • Run and close DRC, LVS, antenna, and density checks on your blocks, and support electromigration and IR drop analysis.
  • Support top-level assembly and chip finishing activities through tape out.
  • Support PIC layout as the need arises, including waveguide and curvilinear structures.
  • Lay out photonic components and waveguide routing — bends, tapers, couplers, grating and edge couplers, and modulator and photodetector electrodes — from designer-provided geometry, honoring minimum bend radius, waveguide spacing, and phase- and length-matching constraints.
  • Run photonics-specific verification: curvilinear DRC against the photonics PDK, waveguide connectivity and port checks, LVS on custom photonic cells, and clean GDS stream-out for tape out.
  • Build the scripts and reusable structures that make the layout team faster.

Qualifications

  • Diploma, BS, or MS in Electrical or Electronics Engineering, or equivalent hands-on layout experience.
  • 1–3 years in custom analog, RF, or mixed-signal IC layout, including at least one tapeout you contributed to through to silicon.
  • Solid working experience with Cadence Virtuoso, including Layout XL and constraint-driven flows.
  • Parasitic awareness in practice — you understand why a matched pair is drawn the way it is, and which nets on your block deserve the extra care.
  • Fundamentals in electromigration and IR drop: current density limits, power routing, and the checks that catch problems.
  • Fundamentals in electromagnetics for on-chip structures — coupling, shielding, and why high-speed routing is constrained the way it is.
  • Physical verification experience: Calibre or PVS DRC/LVS, and parasitic extraction with QRC, StarRC, or equivalent.
  • Some scripting for layout automation — SKILL, Python, or both.
  • Willingness to overlap with US and India hours during tape out crunch.

Skills

Required:Layout for analog/mixed-signal blocksParasitic-aware layout and extractionHigh-speed design and impedance controlPhysical verification (DRC/LVS/Antennas)Scripting for layout automation
Last updated Sep 26, 2026. Interested? Apply on the company site.

About Lumilens

Connectivity Platform for AI

Lumilens provides next-gen photonic interconnects for massively scaling out – and scaling up – AI compute infrastructure.

Photonic InterconnectsNext-Gen ManufacturingSystem-level knowledgeLumicore platformCPO/SiPh manufacturing
Company profileWebsite

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