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Senior/Staff/Principal IC Layout Engineer – Optical Engine Silicon

Lumilens· Engineering
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SingaporeFull-timePosted 4w ago

About the role

Lumilens builds optical interconnect for AI data centers: silicon photonics, mixed-signal ICs, electrical-optical interposers, and the systems around them. You will own layout for electronic ICs (EICs) and photonic ICs (PICs) and support integration of electronic and photonic dies, coordinating with design teams globally from Singapore.

Responsibilities

  • Own floorplan and layout for high-speed analog and mixed-signal blocks: TIAs, drivers, SerDes front ends, PLL and clocking, references and bias.
  • Execute device-level matching and symmetry — common-centroid, dummies, shielding, guard rings, substrate isolation.
  • Route high-speed signal paths with control over impedance, coupling, and return paths. Lay out passive and electromagnetic structures (inductors, transformers, transmission lines) and work with designers through EM simulation.
  • Own chip finishing: pad ring, bump and pillar maps, seal ring, density fill, and top-level assembly through tape out.
  • Drive parasitic-aware layout: iterate with designers on extraction results and close the loop between schematic and layout.
  • Own electromigration and IR drop closure — current density, power grid construction, and analysis for temperature and lifetime.
  • Take blocks through DRC, LVS, antenna, DFM, and ESD and latch-up checks to sign-off.
  • Support PIC layout as needed: waveguide and curvilinear structures, and photonics platform rules.
  • Own layout of photonic blocks: waveguide routing under bend-radius, spacing, length-matching constraints; modulator and photodetector layout co-optimized with RF drive path; grating and edge coupler placement against packaging constraints.
  • Build and maintain the photonic PCell library and PDK integration in Virtuoso — curvilinear geometry generation, SKILL and Python automation, grid snapping and stream-out, DRC/LVS methodology for photonic cells.
  • Own the EIC-PIC integration — micro-bump and pillar alignment, interposer interfaces, and co-layout decisions for cross-die electrical paths.
  • Set layout standards: reusable structures, PDK and tech file evaluation, automation, documentation, and review practice.
  • Mentor junior layout engineers and represent layout in design reviews with authority.

Qualifications

  • Diploma, BS, or MS in Electrical or Electronics Engineering, or equivalent hands-on layout experience.
  • 8+ years in custom analog, RF, or high-speed mixed-signal IC layout, including multiple tape outs to silicon.
  • Expert-level Cadence Virtuoso, including Layout XL and constraint-driven flows.
  • Deep parasitic awareness — ability to map schematics to nets that determine block viability.
  • Working command of electromigration and IR drop fundamentals: current density limits, power grid design, and sign-off checks.
  • Electromagnetics fundamentals for on-chip structures — inductors, transformers, transmission lines, coupling, shielding.
  • Physical verification fluency: Calibre or PVS DRC/LVS, and parasitic extraction with QRC, StarRC, or equivalent.
  • Willingness to overlap with US and India hours during tapeout crunch.

Skills

Required:Layout of high-speed analog and mixed-signal blocksParasitic-aware layout and EM/IR analysisPhysical verification and parasitic extraction
Nice to have:Photonic IC layout
Last updated Sep 26, 2026. Interested? Apply on the company site.

About Lumilens

Connectivity Platform for AI

Lumilens provides next-gen photonic interconnects for massively scaling out – and scaling up – AI compute infrastructure.

Photonic InterconnectsNext-Gen ManufacturingSystem-level knowledgeLumicore platformCPO/SiPh manufacturing
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