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ASIC Engineer, Implementation - Timing

Meta· Design
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Sunnyvale, CA$114k - $172kFull-timePosted 3w ago

About the role

ASIC Implementation Engineer specializing in timing to drive static timing analysis and timing closure for complex SoC designs, ensuring performance, power, and area targets across advanced process nodes in Meta's Infrastructure Silicon team.

Responsibilities

  • Develop and maintain timing constraints (SDC) for complex SoC designs, including clock definitions, input/output delays, multicycle paths, and false paths
  • Perform static timing analysis using industry-standard sign-off tools to identify and resolve setup, hold, and clock skew violations across hierarchical design blocks
  • Drive timing closure through collaboration with physical design engineers, providing guidance on placement, routing, and clock tree synthesis to meet timing targets
  • Analyze and debug timing paths across multiple clock domains, identifying critical paths and recommending RTL or physical implementation optimizations
  • Generate and validate timing reports for sign-off across process, voltage, and temperature corners, including on-chip variation analysis
  • Develop and maintain timing exception methodologies and waiver processes in coordination with design and verification teams
  • Contribute to the development and improvement of timing closure scripts and automation flows using scripting languages to increase efficiency and repeatability
  • Interface with foundry and library teams to characterize and integrate timing libraries, including standard cells, memories, and hard IP
  • Support design handoff between front-end and back-end teams by providing timing-aware synthesis netlists and constraint validation

Qualifications

  • Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
  • 2+ years of experience in ASIC implementation with a focus on static timing analysis and timing closure
  • Experience with industry-standard static timing analysis and sign-off tools such as PrimeTime or equivalent
  • Experience developing and validating SDC timing constraints for complex SoC or IP designs
  • Experience with logic synthesis tools and timing-driven optimization techniques
  • Experience scripting in Python, Tcl, or Perl to automate timing analysis and reporting flows

Skills

Required:Timing constraints (SDC)Static timing analysisClocktree/placement guidanceScripting
Nice to have:RTL/HDL knowledge

Benefits

  • Bonus
  • Equity
  • Benefits
Last updated Oct 23, 2026. Interested? Apply on the company site.

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