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Sr. ASIC Design Engineer (Silicon Engineering)

SpaceX· Silicon Engineering
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Irvine, CA$165k - $265kFull-timePosted 2w ago

About the role

Senior RTL design position focused on developing next-generation ASICs for SpaceX Starlink, collaborating with cross-disciplinary teams to deliver verified, synthesis-ready RTL and enable silicon bring-up and validation for space and ground infrastructure.

Responsibilities

  • Evaluate architectural trade-offs based on features, performance requirements and system limitations
  • Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
  • Work closely with verification team to ensure all aspects of the design are covered and verified
  • Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
  • Participate in silicon bring-up and validation

Qualifications

  • Bachelor’s degree in electrical engineering, computer engineering, or computer science
  • 5+ years of experience in RTL implementation

Skills

Required:RTL implementationArchitectural trade-off evaluationVerification collaborationTiming constraintsSilicon bring-up and validation
Nice to have:clock domain crossings

Benefits

  • comprehensive medical, vision, and dental coverage
  • 401(k) retirement plan
  • short and long-term disability insurance
  • life insurance
  • paid parental leave
  • 3 weeks of paid vacation
  • 10 or more paid holidays per year
  • paid sick leave per company policy
  • employee stock purchase plan (potential equity)
  • discretionary bonuses (potential) and long-term incentives (stock or cash)
Last updated Oct 7, 2026. Interested? Apply on the company site.

About SpaceX

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