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Sr. ASIC Design Engineer (Silicon Engineering)

SpaceX· Silicon Engineering
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Austin, TXFull-timePosted 2w ago

About the role

Senior RTL design engineer role at SpaceX for Starlink, developing next-generation ASICs for space and ground infrastructures, collaborating with cross-disciplinary teams to deliver fully verified, synthesis-timing clean RTL and silicon bring-up.

Responsibilities

  • Evaluate architectural trade-offs based on features, performance requirements and system limitations
  • Define micro-architecture, implement the RTL in Verilog/SystemVerilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
  • Work closely with verification team to ensure all aspects of the design are covered and verified
  • Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
  • Participate in silicon bring-up and validation

Qualifications

  • Bachelor’s degree in electrical engineering, computer engineering, or computer science
  • 5+ years of experience in RTL implementation

Skills

Required:Architectural trade-off evaluationVerilog/SystemVerilogRTL integration and top-level integrationVerification collaborationTiming constraints and physical implementation supportSilicon bring-up and validation
Nice to have:Problem solving (clock domain crossings, power optimization)ASIC/SoC integrationEmbedded CPU subsystemsBus protocols (AXI, AHB, etc.)High-speed and low-power design techniquesScripting (Python, etc.)EDA tools (HDL simulators, HDL lint tools)Team collaboration
Last updated Oct 7, 2026. Interested? Apply on the company site.

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