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Sr. ASIC Design Engineer (Silicon Engineering)

SpaceX· Silicon Engineering
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Hybrid (Redmond, WA)$165k - $270kfull-timePosted 2w ago

About the role

Senior RTL/ASIC design engineer to develop next-generation ASICs for Starlink deployment, collaborating with cross-disciplinary teams to design, verify, and bring-up silicon for space and ground infrastructure.

Responsibilities

  • Evaluate architectural trade-offs based on features, performance requirements and system limitations
  • Define micro-architecture, implement the RTL in Verilog/SystemVerilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
  • Work closely with verification team to ensure all aspects of the design are covered and verified
  • Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
  • Participate in silicon bring-up and validation

Qualifications

  • Bachelor’s degree in electrical engineering, computer engineering, or computer science
  • 5+ years of experience in RTL implementation

Skills

Required:RTL implementationVerilog/SystemVerilog
Nice to have:ASIC/SoC system integrationEmbedded CPU subsystemsBus protocols (AXI/AHB)High speed and low power designScripting (Python)EDA tools (HDL simulators, HDL lint)

Benefits

  • Long-term incentives (stock or long-term cash awards)
  • Discretionary bonuses
  • Employee Stock Purchase Plan
  • Comprehensive medical, vision, and dental coverage
  • 401(k) retirement plan
  • short and long-term disability insurance
  • life insurance
  • paid parental leave
  • 3 weeks of paid vacation
  • 10+ paid holidays per year
  • Paid sick time in accordance with state and federal law
  • Company shuttles for commute from select Seattle locations to SpaceX Redmond office
Last updated Oct 7, 2026. Interested? Apply on the company site.

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