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IP Validation Engineer - Machine Learning Accelerators

Meta· Engineering
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Sunnyvale, CA$178k - $250kFull-timePosted 2w ago

About the role

Reality Labs focuses on on-device AI with custom silicon. The IP Validation Engineer will develop ML accelerator IP validation infrastructure, bring up and validate ML workloads across pre-silicon and post-silicon platforms, and improve functionality, performance, power, and robustness of ML accelerators, partnering cross-functionally with RTL, verification, emulation, architecture, ML compiler, firmware/runtime, and ML model teams.

Responsibilities

  • Define and execute HW-SW integration, functional validation, and characterization plans for ML accelerator IP across emulation, prototyping, and silicon platforms
  • Identify risks and develop mitigation strategies
  • For new technologies and features, work closely with design engineering on defining performance-power characterization and validation strategy, as well as detailed test plans
  • Participate in design reviews and make recommendations to support overall test strategy
  • Create test setups, collect and analyze data to help debug technical issues
  • Partner with RTL design, design verification, emulation, SoC architecture, ML compiler, firmware/runtime, and system teams to bring up ML workloads, identify root causes, drive cross-layer issues to resolution, and verify fixes
  • Convert large amounts of data into a clear summary to communicate to stakeholders at all levels

Qualifications

  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 8+ years of relevant experience in consumer electronics or related fields
  • Experience creating validation plans for hardware products including developing test methodologies for new features and technologies
  • Experience with HW-SW integration and validation of ML accelerators or related programmable compute IP, including workload bring-up, functional debug, performance characterization
  • Experience with common SOC HW interfaces such as AXI, APB, AHB, OCP
  • Experience in troubleshooting with component vendors on test escapes, missing test coverage, etc

Skills

Required:Validation planning

Benefits

  • Benefit information not specified in the provided text; see Meta benefits page for details
Last updated Oct 23, 2026. Interested? Apply on the company site.

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