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ASIC Engineer, Foundry and IP

Meta· Design
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Hybrid (Sunnyvale, CA)$146k - $209kFull-timePosted 2w ago

About the role

Meta seeks an ASIC Engineer, Foundry and IP to design and optimize high-performance, power-efficient ASICs, focusing on foundry benchmarking, PPA analysis, stdcell design, memory compilers, and test chip development.

Responsibilities

  • Analyze and benchmark foundry process offering with physical design teams to identify optimal technologies for product roadmaps
  • Drive early PPA evaluation of foundation IP drops by running preliminary PnR experiments to identify issues and opportunities for improvement
  • Architect, design, and characterize high-performance, low-power, and ultra-high-density standard cell libraries with foundry partners and Physical design teams
  • Run transistor-level simulations (SPICE), direct custom physical layouts, and manage automated library characterization flows
  • Evaluate, benchmark, and choose third-party memory compilers (SRAM, Register Files, ROM) based on rigorous PPA and trade-off metrics
  • Participate in physical implementation, and tape-out of silicon test chips targeted at proving out new foundation IP, custom structures

Qualifications

  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 6+ years of experience in a foundry team driving PPA analysis and engineering army benchmarking
  • Deep understanding of CMOS device physics, digital circuit design, and advanced node layout constraints
  • Proven track record of participating in test chip tapeouts. Hands-on experience in owning end to end design and sign-off of partitions on a test chip
  • Expert-level command of design environments like Cadence Virtuoso, HSPICE, Spectre
  • Working knowledge of synthesis, PnR, STA and PDV tools to converge a block on a test chip
  • High proficiency in scripting with Python, TCL, Perl, or SKILL to automate large-scale evaluation pipelines and data analysis

Skills

Required:Foundry PPA analysisStandard cell design and characterizationCMOS device physicsTest chip tapeoutCadence VirtuosoHSPICE/SpectrePython/TCL/Perl/SKILL scripting

Benefits

  • Benefits information is listed in the posting and may include health, retirement, and other perks; see the job page for details
Last updated Oct 23, 2026. Interested? Apply on the company site.

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