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ASIC Engineer Intern, Design

Meta· Hardware
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Hybrid (Bangalore)InternPosted 2w ago

About the role

Internship role within Meta's Infrastructure organization focusing on ASIC design and verification to build data center accelerators. Opportunity to participate in design and verification of advanced IPs, optimize power/performance/area, and contribute to verification infrastructure and post-silicon validation. Internship duration: 12 to 16 weeks.

Responsibilities

  • Participate in Micro-architecture, Design, and Verification reviews and provide feedback
  • Design and develop RTL or HLS code for some of the IPs
  • Analyze designs and enhance PPA (Power, Performance, Area)
  • Support and develop Verification Infrastructure, analyze and improve Verification Coverage
  • Support Simulation accelerators and post-Silicon validation

Qualifications

  • Currently has, or is in the process of obtaining, a Bachelor's degree in Electrical Engineering, Computer Engineering or related engineering fields
  • Knowledge of Verilog or System Verilog or HLS
  • Knowledge of Computer Architecture and Logic Design fundamentals
  • Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment
  • Intent to return to degree-program after the completion of the internship/co-op

Skills

Required:Verilog/SystemVerilogHLS (High-Level Synthesis)Computer ArchitectureRTL/HDL DesignVerificationSimulation/Post-Silicon Validation
Nice to have:Python/Perl Scripting
Last updated Oct 23, 2026. Interested? Apply on the company site.

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