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Hardware Engineer, PCB Layout

Meta· Engineering
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Menlo Park, CA$173k - $245kFull-timePosted 2w ago

About the role

Staff PCB Layout Engineer responsible for driving design and delivery of complex PCBs for Meta's data center and infrastructure hardware, defining layout architecture and standards, and collaborating across engineering, manufacturing, and supply chain to ensure reliability and performance at scale.

Responsibilities

  • Define PCB layout architecture and floorplanning strategies for complex, high-layer-count boards used in infrastructure and data center hardware
  • Establish and own PCB design rules, constraints, and layout guidelines for high-speed interfaces including PCIe, DDR, Ethernet, and SerDes
  • Lead signal integrity and power integrity analysis in collaboration with electrical engineering teams, driving layout decisions based on simulation results
  • Drive design-for-manufacturability reviews with contract manufacturers and PCB fabricators to ensure yield, reliability, and cost targets are met
  • Define and maintain organization-wide PCB layout standards, templates, and best practices adopted across infrastructure hardware programs
  • Collaborate with mechanical engineers to resolve board-level packaging constraints, thermal management requirements, and enclosure integration challenges
  • Provide technical guidance to other layout engineers across multiple concurrent infrastructure hardware programs
  • Partner with supply chain and component engineering teams to evaluate and qualify alternative components and footprints
  • Lead post-layout verification activities including design rule checks, electrical rule checks, and pre-production board bring-up support
  • Evaluate and introduce new EDA tooling, layout methodologies, and fabrication technologies to improve design quality and cycle time

Qualifications

  • 8+ years of experience in PCB layout design for high-speed digital systems, including boards with DDR, PCIe, or high-speed SerDes interfaces
  • 8+ years of experience with industry-standard EDA layout tools such as Cadence Allegro, Mentor Xpedition, or equivalent
  • Experience defining PCB stack-up configurations, impedance control strategies, and design rule constraints for high-layer-count boards
  • Experience collaborating with signal integrity and power integrity teams to translate simulation results into layout implementation decisions
  • Experience leading PCB layout efforts across the full product development lifecycle from schematic capture through manufacturing release

Skills

Required:PCB layout designSignal integrityDesign for manufacturabilitySchematic capture
Last updated Oct 23, 2026. Interested? Apply on the company site.

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