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DPU IO Architect, Infrastructure Silicon

Meta· Hardware
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Hybrid (Sunnyvale, CA)$178k - $250kFull-timePosted 2w ago

About the role

Meta is seeking a DPU IO Architect to own the I/O subsystem and the hardware/software interface between its DPUs and software, including PCIe, DMA, I/O virtualization, confidential computing, and system management. The role involves defining hardware/firmware/software boundaries, interfaces, and bring-up, and collaborating with firmware, driver, and RTL teams from concept to silicon validation.

Responsibilities

  • Own the I/O subsystem architecture for our DPUs - PCIe, DMA and offload engines, I/O virtualization, confidential computing, and system management -- from early path-finding through silicon bring-up
  • Decide what runs in hardware, what runs in firmware, and what stays in host software, and design the interfaces between them
  • Define the hardware/software interface - register and programming models, descriptor and doorbell interfaces, error and interrupt models, and the offload interfaces firmware and drivers build on
  • Work closely with firmware, driver, and software teams so the interface is clean, efficient, and genuinely usable, and evolve it as their needs change
  • Weigh the performance, power, and area trade-offs behind your choices and back them with data, partnering with performance modeling where deeper analysis is needed
  • Work closely with design, DV, and PD teams on feature definition and PPA tradeoff; refine architecture to meet the design and PD constraints. Define architecture to maximize DV complexity including defining specific features to help ease DV
  • Support Design, DV and PD to resolve interface and integration issues as they come up. Support post-silicon bring-up of the I/O subsystem

Qualifications

  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 8+ years of relevant industry experience architecting I/O and system subsystems and their hardware/software interfaces - register and programming models, DMA and descriptor interfaces, doorbells, and offload interfaces - for NIC/DPU or comparable ASICs
  • Experience with PCIe data link and transport protocols, including TLP formats, transaction types (posted/non-posted/completions), and ordering rules
  • Experience with I/O virtualization technologies such as SR-IOV and SIOV
  • Experience with PCIe capabilities such as Advanced Error Reporting, Downstream Port Containment, and Integrity and Data Encryption
  • Experience with on-chip scheduling and arbitration architectures and quality-of-service mechanisms - transaction/packet schedulers, arbiters, traffic shapers, and rate limiters (meters/policers, token buckets) - and their impact on latency, fairness, bandwidth partitioning, and throughput
  • Experience with symmetric and asymmetric cryptography concepts and inline data encryption (e.g., AES-XTS, AES-GCM)
  • Experience with x86 and/or ARM system architecture, including virtualization technologies, IOMMUs, and interrupt virtualization
  • Experience with data center workloads and their I/O characteristics
  • Experience driving architectural decisions independently and influencing their direction through data

Skills

Required:PCIe knowledgeI/O virtualizationHardware/software interface design

Benefits

  • Bonus
  • Equity
  • Benefits
Last updated Oct 23, 2026. Interested? Apply on the company site.

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