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DPU Power Architect, Infrastructure Silicon

Meta· Hardware
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Hybrid (Sunnyvale, CA)$178k - $250kFull-timePosted 2w ago

About the role

Power Architect to drive power modeling, analysis, and architectural power optimization of DPU designs within Meta’s Infrastructure Silicon organization, influencing architecture from early path-finding through RTL/gate-level power analysis and silicon correlation to deliver strong performance-per-watt on data center workloads.

Responsibilities

  • Analyze and characterize real-world DPU software use cases to identify hardware power bottlenecks and power-relevant behaviors
  • Build and maintain workload-driven, system-level power models and power rollups for current and future SmartNIC/IPU/DPU architectures, tracking accuracy from early analytical estimates through RTL and gate-level power analysis
  • Quantify architectural and micro-architectural trade-offs with respect to PPA, emphasizing energy-per-transaction, power-per-bit moved, and performance-per-watt
  • Define and drive structural power-saving architecture features (DVFS, AVS, power gating, clock gating, activity throttling, power state management, workload-aware power policies)
  • Analyze SoC pipelines and data movement paths to understand and optimize power-versus-performance trade-offs
  • Own power budgets and provide power-delivery and thermal inputs in partnership with design, physical design, firmware, platform, and software teams
  • Correlate pre-silicon power projections with post-silicon measurements and drive methodology improvements

Qualifications

  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • Experience in workload analysis and characterization, and abstracting power-relevant behaviors into models for architectural analysis
  • Experience building system-level power models and power rollups, and tracking them from early estimates through RTL/gate-level power
  • Experience defining or evaluating architectural power-saving features such as DVFS, power gating, and clock gating
  • Understanding of SoC pipelines and how data movement impacts power versus performance
  • Proficiency in programming languages for model development and automation (e.g., Python, C/C++, SystemC)
  • Experience driving analysis independently and influencing architectural direction through data

Skills

Required:Workload analysisSystem-level power modelingPower-saving featuresSoC/power-performance understandingProgramming for models

Benefits

  • Benefits information referenced in posting.
  • Note: Specific benefits are described in Meta benefits page linked in job description.
Last updated Oct 23, 2026. Interested? Apply on the company site.

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