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ASIC Engineer, Formal Verification

Meta· Hardware
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BangaloreFull-timePosted 2w ago

About the role

Meta is hiring an ASIC Formal Verification Engineer to build IP and SoCs for data center applications. The role focuses on developing formal test plans, driving formal verification sign-off for complex blocks, and collaborating with cross-functional teams (software, hardware, ASIC design, emulation, and post-silicon) to enable first-pass silicon success.

Responsibilities

  • Propose, implement and promote the Formal Verification Methodology to be used across the group, both at the top level and at the block level
  • Work with Architecture and Design teams to come up with Formal Verification specification and implementation
  • Define Formal Verification scope, create Formal environment and close coverage with targeted Formal Verification Techniques at IP, Subsystem and SoC level
  • Build reusable/scalable environments for Formal Verification and deploying tools
  • Evaluate and recommend EDA solutions for Formal Verification

Qualifications

  • Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience
  • 2+ years of experience in formal verification
  • Experience with Formal Verification applications including datapath, sequential equivalence, Xprop, Clock Gating, connectivity etc
  • Experience with formal verification methodologies, complexity reduction techniques, and abstraction techniques
  • Experience partnering with architecture, design, and validation teams to define formal verification scope and drive sign-off
  • Fluency in hardware description languages, such as SystemVerilog and SVA
  • Proficiency in scripting languages such as Python, Perl, or Tcl
  • Experience with JasperGold or VC-Formal

Skills

Required:Formal VerificationSystemVerilogSVAPython/Perl/Tcl
Last updated Oct 23, 2026. Interested? Apply on the company site.

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