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Sr. ASIC Design Engineer (Silicon Engineering)

SpaceX· Silicon Engineering
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Palo Alto, CA$175k - $280kfull-timePosted 1w ago

About the role

Senior RTL/ASIC design engineer to develop next-generation ASICs for SpaceX Starlink, working with cross-disciplinary teams to design, implement, verify, and bring up silicon for space and ground infrastructure.

Responsibilities

  • Evaluate architectural trade-offs based on features, performance requirements and system limitations
  • Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
  • Work closely with verification team to ensure all aspects of the design are covered and verified
  • Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
  • Participate in silicon bring-up and validation

Qualifications

  • Bachelor’s degree in electrical engineering, computer engineering, or computer science
  • 5+ years of experience in RTL implementation

Skills

Required:RTL implementation
Nice to have:clock domain crossingASIC/SoC system integrationembedded CPU subsystemsbus protocolshigh speed and low power designscriptingEDA tools

Benefits

  • long-term incentives, stock or long-term cash awards
  • discretionary bonuses
  • Employee Stock Purchase Plan
  • comprehensive medical, vision, and dental coverage
  • 401(k) retirement plan
  • short and long-term disability insurance
  • life insurance
  • paid parental leave
  • paid vacation (3 weeks)
  • 10+ paid holidays per year
  • paid sick leave per company policy
  • other discounts and perks
Last updated Oct 14, 2026. Interested? Apply on the company site.

About SpaceX

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