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ASIC Design Engineer Intern

Meta· Engineering
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Sunnyvale, CA$6.7k/mo - $12k/moInternPosted 1w ago

About the role

Internship in ASIC design within Meta's Infrastructure organization. Participation in design and verification of advanced IPs, micro-architecture reviews, RTL/HLS development, and verification infrastructure to build power-efficient data center accelerators. 12-week program.

Responsibilities

  • Participate in Micro-architecture, Design, and Verification reviews and provide feedback
  • Design and develop RTL or HLS code for some of the IPs
  • Analyze designs and enhance PPA (Power, Performance, Area)
  • Support and develop Verification Infrastructure, analyze and improve Verification Coverage
  • Support Simulation accelerators and post-Silicon validation

Qualifications

  • Currently has, or is in the process of obtaining, a Bachelor's degree in Electrical Engineering, Computer Engineering or related engineering fields
  • Knowledge of Verilog or System Verilog or HLS
  • Knowledge of Computer Architecture and Logic Design fundamentals
  • Must obtain work authorization in country of employment at the time of hire, and maintain ongoing work authorization during employment
  • Intent to return to full-time degree program after completion of the internship

Skills

Required:Verilog/SystemVerilog or HLSComputer Architecture and Logic Design fundamentalsRTL / HLS development
Nice to have:Verification and Verification Infrastructure

Benefits

  • Benefits are provided in addition to base compensation (see posting)
Last updated Oct 23, 2026. Interested? Apply on the company site.

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