Senior/Staff Software Engineer, ML Training Optimization
Hybrid (Foster City, CA / Seattle, WA)$254k - $350kFull-timePosted 5d ago
About the role
Role focused on ML training optimization for large-scaleFoundation models, VLMs, and VLAs to accelerate autonomous driving training. Lead technical direction for distributed training, parallelism, mixed-precision, and RL on accelerators; mentor engineers and shape the team’s roadmap.
Responsibilities
- Lead the design, implementation, and operation of training performance optimizations (data/tensor/pipeline parallelism, mixed precision, gradient checkpointing, GPU kernels) to scale VLM, VLA, and Foundation model training.
- Own the technical strategy and multi-quarter roadmap for RL framework and RL performance optimization for driving foundation models.
- Drive profiling and root-cause analysis of throughput bottlenecks across the compute, compiler, framework, and cluster-networking stack.
- Partner with ML researchers, data engineers, and hardware engineers to define requirements and make architectural decisions for large-scale training infrastructure.
- Build custom kernels and benchmarks that track and validate performance gains across the stack.
- Mentor engineers and raise the team’s technical bar through design reviews and best practices.
Qualifications
- 7+ years of total experience, including 4+ years on large-scale model training platforms, with a record of leading projects end to end.
- Deep experience with distributed training frameworks (Megatron-LM, TorchTitan) and efficiently utilizing GPU/accelerator clusters at scale.
- Experience with RL frameworks (Verl/MILES) and algorithms (GRPO, PPO).
- Experience with collective communication libraries (e.g., NCCL) and optimizing communication/compute overlap in multi-node training.
- Strong command of profiling tools (NVIDIA Nsight, PyTorch Profiler, or XLA/JAX profiling) to find and resolve training bottlenecks.
- Proficiency in Python or C++.
- Experience with ML compilers, performance tooling, or hardware/software co-design (GPU/TPU/accelerator architectures).
- Ability to influence across teams and communicate technical tradeoffs to both researchers and engineers.
Skills
Required:Distributed training frameworksRL frameworks and algorithmsGPU/accelerator clustersProfiling and performance optimizationPython or C++
Last updated Oct 21, 2026. Interested? Apply on the company site.
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