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ASIC Engineer, Implementation

Meta· Engineering
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Sunnyvale, CA$178k - $250kFull-timePosted 4d ago

About the role

Staff ASIC Implementation Engineer responsible for end-to-end physical implementation and synthesis of complex custom ASICs from RTL to tape-out, partnering with design, verification, and physical design teams to deliver high-performance, power-efficient silicon at scale.

Responsibilities

  • Lead end-to-end ASIC implementation flows, including logic synthesis, static timing analysis, formal verification, and design-for-test integration for complex custom silicon designs
  • Define and own synthesis and implementation methodology, establishing reusable flows and constraints that scale across multiple chip projects
  • Drive timing closure strategies across hierarchical design partitions, resolving critical path bottlenecks through collaboration with RTL designers and physical design engineers
  • Develop and maintain synthesis scripts, constraint files, and automation infrastructure to improve implementation quality and reduce iteration cycles
  • Generate SOC floorplans at the chip level, subsystem level, block level and enable block implementation owners to execute on synthesis & physical design
  • Perform top-level logical and physical connectivity and beachfront analysis, including pipe/shim and feedthrough block insertion for timing and area optimisation
  • Partner with architecture and RTL teams to provide early feedback on design decisions that impact area, power, and timing outcomes
  • Define and enforce design rules and quality sign-off criteria across implementation milestones, ensuring readiness for tape-out
  • Identify and drive the resolution of cross-functional implementation risks, communicating status and trade-offs to engineering leadership and program stakeholders
  • Mentor other engineers on implementation methodology, synthesis best practices, and timing analysis techniques
  • Contribute to long-term silicon implementation strategy, evaluating new EDA tools, flows, and technologies to advance Meta's custom chip capabilities

Qualifications

  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 8+ years of experience in ASIC implementation, including logic synthesis, static timing analysis, and timing closure for complex SoC or custom ASIC designs
  • Experience with industry-standard synthesis and implementation EDA tools such as Synopsys Design Compiler, Fusion Compiler, or Cadence Genus
  • Experience defining and managing synthesis constraints including SDC, UPF, and hierarchical design methodologies
  • Experience driving timing closure across multi-million gate designs with multiple clock domains and complex timing exceptions
  • Experience developing and maintaining implementation automation using scripting languages such as Tcl or Python

Skills

Required:Logic synthesisStatic timing analysisTiming closureSynthesis constraintsEDA toolsAutomation scripting

Benefits

  • Bonus
  • Equity
  • Benefits
Last updated Oct 23, 2026. Interested? Apply on the company site.

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