Senior DFT Engineer
NVIDIA· Engineer, ASIC
Santa Clara, CA$136k - $218.5kFull-timePosted 7mo ago
About the role
Design-for-Test Engineering at NVIDIA focuses on DFT architecture, verification and post-silicon validation for complex semiconductor chips. Responsibilities include implementing state-of-the-art test access mechanisms, BIST, scan compression, developing DFT methodologies, and mentoring junior engineers.
Responsibilities
- Own and work with cross functional teams to implement test access mechanisms, IO BIST, memory BIST and scan compression.
- Develop and deploy DFT methodologies for next-generation products.
- Mentor junior engineers on test designs and trade-offs including cost and quality.
Qualifications
- BSEE (or equivalent experience) with 5+ years or MSEE with 3+ years or PhD in DFT or related domains
- Demonstrated knowledge in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation
- Excellent analytical skills in verification and validation of test patterns and logic on complex multi-million gate designs using vendor tools
- Exposure to RTL & clocks design, STA, place-n-route and power to ensure trade-offs
- Experience in Silicon debug and bring-up on the ATE with understanding of pattern formats, failure processing, and test program development
- Strong programming/scripting skills in Perl, Python or Tcl
- Exceptional written and oral communication skills and curiosity to tackle rare challenges
Skills
Required:DFT concepts (scan, BIST, fault modeling)Verification and validation
Nice to have:RTL & clocks design, STA, place-n-route and powerSilicon debug on ATEProgramming/scripting
Benefits
- Equity
- Benefits package (various, as per company policy)
Last updated Oct 2, 2026. Interested? Apply on the company site.
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