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Senior Physical Verification Engineer

NVIDIA· Engineer, ASIC
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Full-timePosted 3d ago

About the role

Lead signoff-quality verification for advanced silicon programs, driving physical verification strategy and closure across implementation, methodology, and signoff teams to achieve tapeout readiness.

Responsibilities

  • Own physical verification closure for major blocks or full-chip designs through tapeout.
  • Lead debugging of complex DRC, LVS, and reliability-related issues and drive high-quality resolution.
  • Define verification check plans, signoff criteria, and closure priorities with cross-functional teams.
  • Partner with physical design, custom design, and CAD teams to improve quality and turnaround.
  • Drive automation, methodology improvements, and best practices for scalable PV execution.
  • Review results, coach team members, and help reduce repeated classes of violations.

Qualifications

  • B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or equivalent experience.
  • 5+ years of experience in physical verification, backend implementation, or ASIC signoff.
  • Deep knowledge of DRC, LVS, physical signoff methodology, and tapeout flows.
  • Strong experience with industry-standard physical verification tools and foundry rule decks.
  • Proven ability to debug and close complex verification issues on large designs.
  • Strong scripting and automation skills.
  • Excellent communication and cross-team execution skills.

Skills

Required:Physical verification
Last updated Oct 23, 2026. Interested? Apply on the company site.

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