Senior Digital Design Verification Engineer - Hardware
NVIDIA· Engineer, ASIC Mixed Signal Design
Santa Clara, CA$136k - $218.5kfull-timePosted 7mo ago
About the role
Senior Digital Design Verification Engineer to verify SerDes IPs using advanced methodologies (e.g., UVM) and develop verification infrastructure for product-shipment focused timelines at NVIDIA.
Responsibilities
- Verification of the digital design, golden models and micro-architecture of the SerDes IPs using advanced verification methodologies such as UVM.
- Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
- Responsible for understanding the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
- Write and implement test plan and thoroughly verify a design in a product shipment focused / compressed schedule.
- Work with architects, designers, and pre and post silicon verification teams to accomplish your tasks.
Qualifications
- Bachelors or Masters Degree (or equivalent experience) in Electrical Engineering, Computer Science, or Computer Engineering
- At least 5 years of validated experience
- Background in verification at Unit/Sub-system/SOC level and expertise in SystemVerilog
- Experience using random stimulus along with functional coverage and assertion-based verification methodologies
- Experience in verification methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug.
Skills
Required:SystemVerilogUVM/VMMrandom stimulusfunctional coverageassertion-based verification
Benefits
- equity
- benefits
Last updated Jul 3, 2026. Interested? Apply on the company site.
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