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Senior Mask Layout Design Engineer

NVIDIA· Engineer, Mask Design
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Hybrid (Santa Clara, CA), Hybrid (Remote)$132k - $207kfull-timePosted 7mo ago

About the role

Senior Mask Layout Design Engineer responsible for multi-disciplinary collaboration, physical layout of digital and mixed-signal functions in sub-micron CMOS technologies, and DRC/LVS verification, with leadership responsibilities and collaboration across geographies.

Responsibilities

  • Perform physical layout for digital and mixed-signal functions like clock generators, op-amps, sensors, security circuits, power delivery circuits in state-of-the-art sub-micron CMOS technologies using Cadence tools
  • Work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products
  • Floor planning, custom layout and verifying against design rules and schematics
  • Fill, post-processing, DRC mitigation, and foundry interactions
  • Collaborate with a multi-disciplinary team of Circuit designers and mask designers
  • Mentor junior mask designers, implement standard processes for the team, and maintain checklists for optimal layout design

Qualifications

  • BS in Electrical Engineering (or equivalent experience)
  • At least 7+ years of hands-on layout design experience
  • Deep understanding of analog circuit layout concepts in submicron CMOS technologies
  • Validated experience with Cadence custom circuit design tools - particularly virtuoso
  • Experience running and debugging DRC and LVS with verification tools such as Dracula, Hercules, Calibre
  • Leadership experience mentoring and assisting junior mask designers, implementing standard processes for the team, and keeping checklists for optimal layout design
  • Communicate with diverse team of mask designers across geographies and timezones
  • Ability to work optimally in a team, good interpersonal skills and positive energy
  • Proficiency in scripting languages like Perl, Python; Skill etc. is a plus
  • Knowledge of layout automation is a definite plus

Skills

Required:Electrical Engineering fundamentalsAnalog circuit layoutCadence VirtuosoDRC/LVS verificationLeadership/mentoring
Nice to have:ScriptingLayout automation

Benefits

  • equity
  • benefits (see company link)
Last updated Jul 3, 2026. Interested? Apply on the company site.

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