← All roles

Senior Logic Design Engineer, Cache Coherent Interconnects

NVIDIA· Engineer, ASIC
Apply on company site
Hybrid (Santa Clara, CA), Hybrid (Hillsboro, OR)$136k - $218.5kFull-timePosted 7mo ago

About the role

Senior Logic Design Engineer responsible for design of CPU interconnects, caches, and coherency mechanisms, including RTL coding, timing closure, verification collaboration, and optimization for power and performance.

Responsibilities

  • Own and deliver a specific unit on the chip as part of the core CPU team
  • Write readable high performance and low power RTL, perform synthesis and timing closure, and document design
  • Collaborate with verification team to verify unit correctness
  • Work with implementation to meet timing, area, performance and power goals
  • Assist with timing closure of super units

Qualifications

  • Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience
  • 5+ years of experience in processor or other related high performance semiconductor designs
  • Verilog expertise and deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug
  • Strong communication and interpersonal skills; mentoring junior engineers and interns a plus
  • Strong background in computer architecture, cache coherency or high speed interconnects (helpful)

Skills

Required:VerilogASIC design flowCommunication and mentoring
Nice to have:Computer architecture

Benefits

  • equity
  • benefits (as per company)
Last updated Jul 3, 2026. Interested? Apply on the company site.

About NVIDIA

World Leader in AI Computing

NVIDIA invents the GPU and drives advances in AI, HPC, gaming, creative design, autonomous vehicles, and robotics.

AIautonomous vehiclesgaminggpugraphics cardhigh performance computingliquid-ai-recruiting-targetllm
Company profileWebsite

More open roles at NVIDIA