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GPU/SOC Low-Power Feature Architect

NVIDIA· Engineer, ASIC
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Hybrid (Multiple US locations and remote)$168k - $264.5kfull-timePosted 7mo ago

About the role

Engineer in NVIDIA Silicon Co-Design Group HW ArchDev to design and optimize high-speed interconnects (NVLink/NVLink-C2C), focusing on IO power optimizations, system interoperability, and cross-team collaboration across next-generation products.

Responsibilities

  • Contribute to the design of the next generation of high-speed IOs, including NVLink and NVLink-C2C.
  • Responsible for IO power optimizations and continuing to push energy efficiency.
  • Ensure interoperability with connected devices and system components in complex interconnect topologies
  • Deep dive into technically challenging HSIO bugs and help drive debug efforts across various teams
  • Work closely and proactively with other engineering teams such as system architects, mixed signal and design, DGX, software/firmware, HW/SW QA, operations, and AE teams to drive design, development, debug, and release of next-generation products.

Qualifications

  • BS or MS degree in EE/CE or equivalent experience
  • Minimum 10 years working on capacity - power management, use case analysis, perf/power modeling, bringup, and/or debug.
  • Experience with system-level and interconnect power management optimizations
  • Silicon and platform-level power modeling for active/idle use cases
  • Understanding of firmware/driver structures and their interaction with HW
  • Track record of influence, leadership, and collaboration across multiple teams towards a unified goal
  • Strong EE fundamentals, knowledgeable in computer architecture, high-speed interfaces, timing analysis, process variations, statistical error rates, and power analysis.

Skills

Required:High-speed IO design and interconnectsIO power optimizationSystem interconnect interoperability

Benefits

  • equity
  • benefits (per company)
Last updated Oct 2, 2026. Interested? Apply on the company site.

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