Senior Physical Design and Timing Engineer
NVIDIA· Engineer, ASIC
Westford, MA$168k - $264.5kfull-timePosted 7mo ago
About the role
Senior ASIC Timing Design Engineer role at NVIDIA focusing on physical design and timing for high-frequency DPUs/SoCs, with emphasis on RTL-to-GDS2 flow, STA, timing constraints, and ECO implementations within networking silicon.
Responsibilities
- Drive physical design and timing of high-frequency and low-power DPUs and SoCs at block level, chiplet level, and/or full chip level.
- Analyze and optimize design constraints and synthesis parameters to achieve performance, power, and area targets.
- Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.
Qualifications
- BS (or equivalent experience) in Electrical or Computer Engineering with 8 years experience or MS with 4+ years experience in Synthesis and Timing
- Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence
- Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis
- Expertise in physical design and optimization e.g., placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power, along with a background in implementing them through ECOs
- Background in logic synthesis and/or logical equivalence checking (LEC)
- Expertise and in-depth knowledge of industry standard EDA tools (Synopsys PrimeTime or Cadence Tempus)
- Proficiency in Python, Tcl and Make for automation and scripting tasks
Skills
Required:Static Timing Analysis (STA)Timing constraintsECO implementationDesign optimizationSynthesis/LECEDA toolsAutomation scripting
Benefits
- equity
- benefits
Last updated Oct 23, 2026. Interested? Apply on the company site.
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