Senior ASIC Design Engineer
NVIDIA· Engineer, ASIC
Santa Clara, CA$168k - $264.5kFull-timePosted 7mo ago
About the role
Senior ASIC Design Engineer to implement high performance, power-efficient RTL for GPUs/SoCs, collaborating across silicon teams from architecture to back-end verification, with exposure to post-silicon validation and debugging.
Responsibilities
- As a key member of the GPU Design team, you will implement, document and deliver high performance, area and power efficient RTL to achieve design targets and specifications.
- Analyze architectural trade-offs based on features, performance requirements and system limitations.
- Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design.
- Collaborate and coordinate with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks.
- Work on a broad list of IPs such as GPU's work scheduler, time distribution system, interrupt controllers, and DMA engines.
- Architect features to help silicon debug and support post-silicon validation activities.
Qualifications
- Bachelors Degree or equivalent experience in Electrical Engineering, Computer Engineering or Computer Science.
- 8+ years of meaningful work experience.
- Experience in micro-architecture and RTL development (Verilog), focused on arbiters, scheduling, synchronization & bus protocols, interconnect networks and/or caches.
- Great understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis.
- Exposure to Digital systems and VLSI design, Computer Architecture, and Computer Arithmetic is required.
- Strong interpersonal skills and an excellent teammate.
Skills
Required:Verilog RTLMicro-architectureASIC design flowDigital systemsComputer Architecture
Benefits
- equity
- benefits (as listed in job description)
Last updated Oct 23, 2026. Interested? Apply on the company site.
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