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ASIC Design Verification Engineer - New College Grad 2026

NVIDIA· Engineer, Verification
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Hybrid (Austin, TX)$116k - $189.8kfull-timePosted 7mo ago

About the role

Entry-level ASIC verification engineer focusing on system-level IP verification, developing and maintaining verification environments, UVM-based testbenches, and improving verification methodologies for RTL designs.

Responsibilities

  • Design and maintain the unit level/sub-system Verification environment.
  • Understand the architecture specifications, develop and carry out the test plan to verify the design.
  • Create the UVM components, sequences, tests and scoreboards.
  • Sign off on the verification efforts with very high quality code and functional coverage.
  • Launch regressions, resolve the issues, and make forward progress towards achieving the DV milestone targets
  • Automate the manual steps involved in launching build, regression, and triages.
  • Collaborate with architects, designers, and software engineers to achieve the project goals.
  • Pro-actively contribute to improving the efficiency of the testbenches by embracing the latest techniques.

Qualifications

  • Completing an MS or higher in Computer or Electrical Engineering (or equivalent experience).
  • Experience in System Verilog, UVM and in general OOPS based programming.
  • Strong coding skills in Python or other industry-standard scripting languages.
  • Strong understanding of RTL design (Verilog).
  • Good understanding of computer architecture fundamentals.
  • Familiarity with verification tools such as VCS or equivalent simulation tools, and debug tools like Verdi.

Skills

Required:SystemVerilogUVMPythonRTL Design (Verilog)

Benefits

  • equity
  • benefits (as listed)
Last updated Jul 3, 2026. Interested? Apply on the company site.

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