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Senior DFT Engineer - Hardware

NVIDIA· Engineer, ASIC
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BengaluruFull-timePosted 7mo ago

About the role

Senior DFT Engineer focused on DFX testing of high speed IOs for NVIDIA's IO/DFX team,涉及 pre- and post-silicon testing, testplan development, automation, and collaboration with IP, mixed-signal design, and production teams.

Responsibilities

  • POR to Post Silicon Testing of DFX features for high speed IOs. Architect, Design & Validate test features with robust & scalable testplan development at unit-level and SOC/Full Chip level using verification methodologies like UVM and NVIDIA Internal tools. Pre-Silicon Simulation and Debug of Test functionality and sign off on Test coverage for various products using standard coverage metrics.
  • Ability to work on automation, flow development & improvement, coverage metrics, test execution, bug identification/fix and IO-test productization.
  • Solve complex Test problems in the mixed-signal world and develop a scalable test solution across platforms.
  • Work with Design/Verification tools and languages (SV, UVM, Perl, Python) and NVIDIA custom tools/flows.
  • Collaborate with IP teams for IOBIST test-logic design/verification and with Mixed Signal Circuit design teams to understand analog IO cell components. Coordinate with other DFX teams, Post Silicon Test Engineering and Production Engineering for productizing quality test at efficient cost.

Qualifications

  • Btech/BE/BS in EE/ECE or Mtech/ME/MS or equivalent experience
  • Solid Analytical and Problem Solving skills
  • Good understanding of Logic design, Architecture & Verification
  • Strong Coding skills in industry standard scripting languages
  • 3+ years of experience in DFT and/or verification flows (constrained random testing, UVM, coverage metrics, profiling tools, X prop, etc.)
  • Outstanding written and oral communication skills

Skills

Required:DFTUVMScripting (Python, Perl)
Nice to have:Constrained Random Testing
Last updated Jul 3, 2026. Interested? Apply on the company site.

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