Senior Mask Design Engineer - Hardware
NVIDIA· Engineer, Mask Design
Santa Clara, CA$132k - $207k + equityfull-timePosted 7mo ago
About the role
Senior Mask Layout Design Engineer responsible for physical layout of high-speed mixed-signal circuits (e.g., PLLs, SerDes, ADCs, ESD structures) in sub-micron CMOS, using Cadence tools, collaborating with ASIC and mixed-signal teams, and participating in floor-planning, custom layout, and rule/schematic verification.
Responsibilities
- Performing physical layout for mixed-signal functions like PLL's, high speed SerDes, Analog to Digital converters, ESD structures designs in state-of-the-art sub-micron CMOS technologies using Cadence tools.
- You'll work cross functionally with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
- Take part in floor planning, custom layout and verifying against design rules and schematics.
Qualifications
- Have a BSEE or equivalent experience.
- Minimum of 7+ years industry experience in Mask and Layout Design.
- Deep understanding of analog circuit layout concepts in submicron CMOS technologies.
- You are an authority with Cadence custom circuit design tools - particularly virtuoso.
- Experience running and debugging with verification tools such as Dracula, Hercules, Calibre, and Primeyield.
- You are able to work effectively in a team, good interpersonal skills, enthusiasm and positive energy.
- You'll be proficient in scripting languages like perl, python, skill etc.
- Should have knowledge of DRC and LVS checking flows, ability to customize decks.
Skills
Required:BSEE or equivalentMask and Layout DesignAnalog circuit layout (submicron CMOS)Cadence VirtuosoVerification toolsScripting (Perl, Python, Skill)DRC/LVS workflows
Benefits
- equity
- benefits (see NVIDIA benefits page)
Last updated Jul 3, 2026. Interested? Apply on the company site.
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