Senior Mask Design Engineer - Hardware
NVIDIA· Engineer, Mask Design
Santa Clara, CA$132k - $207kFull-timePosted 7mo ago
About the role
Senior Mask Layout Design Engineer responsible for physical layout of mixed-signal functions (PLL, high-speed SerDes, ADC, ESD structures) in sub-micron CMOS technologies, collaborating with ASIC and analog/mixed-signal teams, and ensuring design rule/spec verification.
Responsibilities
- Performing physical layout for mixed-signal functions like PLL's, high speed SerDes, Analog to Digital converters, ESD structures designs in state-of-the-art sub-micron CMOS technologies using Cadence tools.
- Work cross functionally with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
- Take part in floor planning, custom layout and verifying against design rules and schematics.
Qualifications
- Have a BSEE or equivalent experience with Minimum of 6+ proven experience in Mask and Layout Design.
- Deep understanding of analog circuit layout concepts in submicron CMOS technologies.
- Authority with Cadence custom circuit design tools - particularly virtuoso.
- Experience running and debugging with verification tools such as Dracula, Hercules, Calibre, and Prime-yield.
- Able to work optimally in a team, good interpersonal skills, passion and positive energy.
- Proficient in scripting languages like perl, python, skill etc.
- Knowledge of DRC and LVS checking flows, ability to customize decks.
Skills
Required:Cadence VirtuosoAnalog circuit layoutDRC/LVSScriptingVerification tools
Benefits
- equity
- benefits (see benefits page)
Last updated Jul 3, 2026. Interested? Apply on the company site.
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