Senior Verification Engineer, Memory Subsystem
NVIDIA· Engineer, Verification
BengaluruFull-timePosted 7mo ago
About the role
Senior Verification Engineer responsible for verifying the ASIC design, architecture and micro-architecture of NVIDIA's memory subsystem using advanced verification methodologies, with a focus on functional coverage, performance/deadlock verification, and reusable verification infrastructure.
Responsibilities
- Responsible for verifying the ASIC design, architecture and micro-architecture using advanced verification methodologies.
- Understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
- Come up with test plans, tests and verification infrastructure for complex IPs/sub-systems.
- Responsible for performance and deadlock verification of the GPU memory subsystem unit.
- Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
- Perform functional coverage driven verification closure.
- Working with architects, designers, and pre and post silicon verification teams to accomplish tasks.
Qualifications
- B.Tech./ M.Tech. with 4+ years of relevant experience
- Experience in verification of complex IPs/units and sub-systems
- Verification experience using random stimulus along with functional coverage and assertion-based verification methodologies
- Expertise in Verilog
- Knowledge in SystemVerilog or similar HVL
- Familiarity with verification methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug
Skills
Required:VerilogSystemVerilogUVM/VMM
Nice to have:Python/Perl/Shell scripting
Last updated Jul 3, 2026. Interested? Apply on the company site.
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