Senior AI STA Engineer, Sub-chip
NVIDIA· Engineer, ASIC
Yokneam, Beersheva, Tel Avivfull-timePosted 7mo ago
About the role
NVIDIA seeks experienced Physical Design Engineers to advance AI-augmented Static Timing Analysis (STA) for complex chiplets and full-chip designs, focusing on timing optimization, data analysis, and convergence across RTL, DFT, and physical design teams.
Responsibilities
- Perform advanced AI Static Timing Analysis (STA) for complex chiplet and full chip level.
- AI use for timing optimization and data analysis in STA and PnR.
- Running and building STA tools for analysis and debug timing.
- Use traditional STA tools like Prime Time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
- Identify convergence risks and work closely with physical design, RTL and DFT teams, ensuring convergence throughout various project stages.
- Responsible for a full timing closer and quality approval from pre-layout STA model through signoff.
Qualifications
- B.SC./ M.SC. in Electrical Engineering.
- At least 5+ years of hands-on STA experience.
- Experience in Prime Time and signoff methodologies.
- A great teammate who thrives in a collaborative environment.
- AI tools orientation or alternatively a desire to learn.
Skills
Required:Static Timing Analysis (STA)PrimeTimeRTL/DFT collaboration
Nice to have:AI tools for timing/analysisPython / TCL / Bash scripting
Benefits
- Agentic Frameworks.
- AI prompting experience.
- Experience in Linux environments.
- TCL, Python, shell scripting abilities.
- Experience with data collection and analysis.
Last updated Sep 18, 2026. Interested? Apply on the company site.
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