Senior Physical Design Engineer
NVIDIA· Engineer, Phys Design
Westford, MA$136k - $218.5kfull-timePosted 7mo ago
About the role
Senior Physical Design Engineer to lead physical design and implementation of SOC devices for networking markets, participating in partition/chiplet level work and establishing design methodologies, with RTL2GDS lifecycle and timing/verification responsibilities.
Responsibilities
- Lead all aspects of physical design and implementation of SOC devices targeted at the networking markets.
- Work at the partition and chiplet level.
- Participate in establishing physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure.
- Daily work involves all aspects of physical chip development (RTL2GDS) – trial synthesis, power and clock distribution, place and route, timing closure, power and noise analysis and physical verification.
Qualifications
- BSEE / MSEE or equivalent experience.
- 5 years of experience in VLSI physical design implementation on 5nm, 4nm and 3nm technology.
- A successful track record of delivering designs to production.
- Able to assist in design flow development and debugging, including application of ML/AI solutions.
- Validated strong power user of P&R, Timing Analysis, Physical Verification, IR Drop Analysis, CAD tools from Synopsys (ICC2/DC/PT/STAR/ICV), Cadence (Genus/Innovus/Tempus) and other major EDA companies.
- Prior experience in timing closure, clock/power distribution and analysis, RC extraction and correlation, place/route and tapeout solutions.
- Strong analytical and debugging skills.
- Proficiency using Python, Perl, Tcl, Make scripting (helpful).
- Great teammate
Skills
Required:Physical designTiming closurePower/clock distributionRC extraction and correlationRTL2GDSEDA tools
Nice to have:PythonPerlTcl
Benefits
- Equity
- benefits (as listed in company overview)
Last updated Oct 23, 2026. Interested? Apply on the company site.
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