Senior ASIC Design Engineer - NOC IP
NVIDIA· Engineer, ASIC
Bengaluru, IndiaFull-timePosted 7mo ago
About the role
Senior design engineer on NVIDIA’s Graphics team focusing on memory subsystem components for graphics processors. Responsible for architectural trade-offs, micro-architecture, RTL implementation, and fully verified, synthesis/timing-clean designs, collaborating with architects, verification, timing, backend, FPGA/SW, and post-silicon teams.
Responsibilities
- Own micro-architecture and RTL development of design modules.
- Micro-architect features to meet performance, power and area requirements.
- Work with HW architects to define critical features.
- Collaborate with verification teams to verify the correctness of implemented features.
- Co-operate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable.
- Interact with FPGA and S/W teams to prototype the design and ensure that S/W is tested.
- Work on post-silicon verification and debug.
Qualifications
- BS / MS or equivalent experience.
- 7+ years of design experience.
- Experience in RTL design of complex design units for at least two or three projects.
- Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).
- Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
- Expertise in Verilog.
Skills
Required:RTL designVerilogDesign verification
Nice to have:Scripting (Python/Perl/shell)Leadership (2-3 member teams)
Last updated Jul 3, 2026. Interested? Apply on the company site.
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