Senior SRAM Circuit Design Engineer
NVIDIA· Engineer, ASIC
Bengaluru, IndiaFull-timePosted 7mo ago
About the role
Senior SRAM circuit design engineer to develop SRAM macros and SRAM compiler workflows within NVIDIA's Digital IP group, collaborating with SOC design, silicon test, and productization teams to deliver production-ready SRAM IP and compilers.
Responsibilities
- Embedded SRAM design: Transistor-level circuit design, supervising layout implementation, physical and logical verification, and debug of SRAM macros.
- SRAM compiler development: Envisioning, defining, and coding more efficient ways to automate the simultaneous assembly and validation of multiple unique SRAM macros using NVIDIA's extensive compute resources.
- Advanced development: Exploring the potential of future process nodes and developing techniques to achieve optimal power, performance, and area characteristics.
- Guiding SOC design, silicon test, and productization efforts: Collaborate with SOC design partners to help them achieve their overall performance and cost goals, guide the silicon test and characterization efforts, and working with productization teams to prepare new silicon for the demanding requirements of real-world applications.
Qualifications
- BSEE minimum (or equivalent experience), MSEE or PhD preferred
- 5+ years of SRAM design experience with a strong background in digital circuit design, layout, and validation on advanced FinFET processes
- Prior design experience in single-port, dual-port, or register file SRAM-based macros required, including complex circuits like self-timed logic and sense-amplifiers
- Python scripting ability to parse data and automate tasks
- Successful track record of delivering designs to production
Skills
Required:SRAM designSRAM compilerPython scriptingDigital circuit design
Nice to have:Cadence tools
Last updated Jul 3, 2026. Interested? Apply on the company site.
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