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ASIC Design Verification Engineer, Machine Learning

Google
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Sunnyvale, CA, USA$138k - $198kFull-timePosted 6mo ago

About the role

ASIC Design Verification Engineer focusing on verification of complex digital designs for AI/ML hardware acceleration, with emphasis on TPU architecture and integration within AI/ML-driven systems.

Responsibilities

  • Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
  • Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
  • Identify and write all types of coverage measures for stimulus and corner-cases.
  • Debug tests with design engineers to deliver functionally correct design blocks.
  • Close coverage measures to identify verification holes and to show progress towards tape-out.

Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 4 years of experience with design verification.
  • Experience with SystemVerilog/Verilog.

Skills

Required:SystemVerilog/VerilogConstrained-random verificationUVM
Nice to have:Formal verificationProblem solving and communication

Benefits

  • Learn more about benefits at Google
Last updated Oct 23, 2026. Interested? Apply on the company site.

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