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Senior Cell Modeling and Verification Engineer

NVIDIA· Engineer, ASIC
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Santa Clara, CA$136k - $218.5kfull-timePosted 6mo ago

About the role

Senior Cell Modeling and Verification Engineer to develop behavioral models and verification for custom mixed-signal design cells and ensure RTL/design targets are met for NVIDIA’s ASIC/SoC products.

Responsibilities

  • Work with sophisticated technologies and develop behavioral model and verification for custom mixed signal design cells that would be used on all the NVIDIA products.
  • Use Verilog, SystemVerilog, Perl, or Python and understanding of PLL and other high-speed interconnects to model, verify, emulate/prototype mixed-signal designs.
  • Collaborate with cross function teams with regards to library build, cell integration, ASIC verification and DFT simulation.
  • Document, implement, and deliver fully verified and high performance RTL to achieve design targets.

Qualifications

  • Bachelors or Masters in Electrical Engineering or Computer Engineering (or equivalent experience).
  • 3+ years of relevant experiences
  • Hands-on experience with RTL simulation and waveform debug.
  • Strong understanding of Verilog HDL.
  • Scripting experiences and skills using Python or Perl.
  • Knowledge of fundamental digital design and logic design concepts.

Skills

Required:Verilog HDLSystemVerilogRTL simulationPython
Nice to have:Perl

Benefits

  • You will also be eligible for equity and benefits.
Last updated Oct 23, 2026. Interested? Apply on the company site.

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