Physical Design Backend STA Engineer
NVIDIA· Engineer, ASIC
Yokneam, Tel AvivFull-timePosted 6mo ago
About the role
NVIDIA is seeking STA (Static Timing Analysis) Physical Design Engineers to join the Networking team in Israel, focusing on high-speed communication devices with emphasis on timing analysis and convergence across project stages.
Responsibilities
- Perform advanced Static Timing Analysis (STA) at a chiplet and FC level.
- Running Prime Time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
- Identify convergence risks and work closely with physical design, RTL and DFT teams, ensuring convergence throughout various project stages.
- Responsible for a full timing closer and quality approval from pre-layout STA model through signoff.
Qualifications
- B.Sc. in Electrical Engineering or Computer Engineering.
Skills
Required:Static Timing Analysis (STA)PrimeTimeConstraints and sdc generation
Last updated Jul 3, 2026. Interested? Apply on the company site.
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