Senior Verification Engineer, Memory Subsystem
NVIDIA· Engineer, Verification
Bengaluru, IndiaFull-timePosted 6mo ago
About the role
Senior verification engineer responsible for verifying the ASIC design, architecture, and micro-architecture of the GPU memory subsystem using advanced verification methodologies, building verification infrastructure, and ensuring functional and performance correctness.
Responsibilities
- Responsible for verifying the ASIC design, architecture and micro-architecture using advanced verification methodologies.
- Expected to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
- Come up with test plans, tests and verification infrastructure for complex IPs/sub-systems.
- Responsible for performance and deadlock verification of the GPU memory subsystem unit.
- Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
- Perform functional coverage driven verification closure.
- Working with architects, designers, and pre and post silicon verification teams to accomplish your tasks.
Qualifications
- B.Tech./ M.Tech. with 4+ years of relevant experience
- Experience in verification of complex IPs/units and sub-systems
- Verification experience using random stimulus along with functional coverage and assertion-based verification methodologies
- Expertise in Verilog
- Knowledge in SystemVerilog or similar HVL
- Familiarity with verification methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug
Skills
Required:VerilogSystemVerilogUVM/VMMVerification planning
Nice to have:Debugging and analysisPython/Perl/shell scripting
Benefits
- Competitive salaries
- Generous benefits package
- Equal opportunity employer
- Diversity and inclusion policies
Last updated Jul 3, 2026. Interested? Apply on the company site.
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