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Senior Mixed Signal Design Engineer

NVIDIA· Engineer, ASIC Mixed Signal Design
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Taipei, Taiwan, Hsinchu, TaiwanFull-timePosted 5mo ago

About the role

Senior mixed-signal/analog/IO circuit design engineer for high-speed memory interfaces, responsible for taking designs through productization and collaborating with multi-functional teams in a on-site role in Taiwan.

Responsibilities

  • Mixed-Signal/Analog circuit design for High Speed Memory I/O Interfaces
  • Solve challenge of circuit designs in deep submicron CMOS FinFET processes
  • Take designs through productization and be involved in all stages of development
  • Work with multi-functional teams to optimize the designs

Qualifications

  • Advanced High-Speed Design Expertise: 5+ years of proven experience in high-speed memory (LPDDR, DDR, GDDR, HBM) or SerDes design, underpinned by a BSEE or MSEE and a deep understanding of system-level timing budgets and specifications
  • FinFET Circuit Mastery: In-depth technical command of deep submicron CMOS FinFET processes, with the ability to navigate complex circuit design challenges and implementation nuances
  • Reliability & Physical Integrity: Comprehensive knowledge of device reliability, ESD, and Latch-Up requirements, including the ability to supervise layout development to ensure strict adherence to these critical rules
  • Full-Flow Tool Proficiency: Expert-level command of Cadence custom design environments and industry-standard simulators (Hspice, XA, FineSim, Spectre), with a working knowledge of Verilog, Nanotime, or Matlab
  • Silicon-to-System Perspective: Ability to bridge the gap between die and system, offering insights into package substrate design, board-level constraints, and PDN analysis
  • Collaborative Leadership: A proactive teammate with strong interpersonal skills, capable of mentoring junior engineers and performing hands-on validation using high-end lab test and measurement equipment

Skills

Required:High-speed memory/SerDes designFinFET process know-howDevice reliability, ESD, latch-upCadence and simulators
Nice to have:Verilog/Nanotime/MatlabSystem-to-die bridgingMentoring and leadership
Last updated Jul 3, 2026. Interested? Apply on the company site.

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