Senior Performance Modeling Architect, CPU Fabric and LLC
NVIDIA· Architect
Santa Clara, CA$152k - $241.5kFull-timePosted 5mo ago
About the role
Lead architectural definition and improvement of CPU cache hierarchies and interconnects, building high-fidelity performance models to drive scalable, low-latency data path across automotive and data center domains.
Responsibilities
- Developing and maintaining high-fidelity, cycle-accurate performance models (C++/SystemC) for coherent interconnects and large-scale shared caches.
- Modeling and analyzing performance bottlenecks across scales from automotive SoCs to large data center architectures.
- Evaluating performance impact of coherency protocols (e.g., CHI, ACE, or proprietary) and snooping filters.
- Running and analyzing industry-standard benchmarks (SPEC, MLPerf, Automotive-specific suites) to drive architectural trade-offs.
- Collaborating with build and verification teams to correlate performance models with silicon and working with software teams to optimize drivers for the underlying hardware topology.
Qualifications
- Master’s or Ph.D. in Computer Engineering, Electrical Engineering, or Computer Science (or equivalent) with focus on architecture and 5+ years of experience.
- Strong understanding of CPU microarchitecture, memory consistency models, and cache coherency protocols.
- Proven experience in C++ or SystemC for cycle-accurate or functional modeling.
- Proficiency in Python or similar scripting languages for processing large datasets, generating performance visualizations, and automating simulation sweeps.
- Understanding of Network-on-Chip (NoC) topologies (Mesh, Ring, Torus), credit-based flow control, and arbitration logic.
Skills
Required:CPU microarchitectureCycle-accurate modelingProgramming languages
Benefits
- equity
- benefits
Last updated Jun 26, 2026. Interested? Apply on the company site.
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