Senior Mask Design Engineer - Hardware
NVIDIA· Engineer, Mask Design
Santa Clara, CA$132k - $207kfull-timePosted 5mo ago
About the role
Senior Mask Layout Design Engineer responsible for physical layout of mixed-signal circuits (PLL, high-speed SerDes, ADCs, ESD structures) in sub-micron CMOS using Cadence tools, collaborating with ASIC and mixed-signal teams, and ensuring design rule and schematic verification.
Responsibilities
- Performing physical layout for mixed-signal functions like PLL's, high speed SerDes, Analog to Digital converters, ESD structures designs in innovative sub-micron CMOS technologies using Cadence tools.
- Work multi-functional with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
- Take part in floor planning, custom layout and verifying against design rules and schematics.
Qualifications
- BSEE or equivalent experience and minimum of 8+ years industry experience.
- Deep understanding of analog circuit layout concepts in submicron CMOS technologies.
- Authority with Cadence custom circuit design tools.
- Experience running and debugging with verification tools such as Dracula, Hercules, Calibre, and Primeyield.
- Able to work optimally in a team, good interpersonal skills, passion and positive energy.
- Proficient in scripting languages like Perl, Python, etc.
- Knowledge of DRC and LVS checking flows, ability to customize decks.
Skills
Required:Analog circuit layoutCadence toolsVerification toolsScripting
Benefits
- equity
- benefits (see NVIDIA benefits)
Last updated Jul 3, 2026. Interested? Apply on the company site.
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