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Senior Photonic Layout Design Engineer

NVIDIA· Engineer, Mask Design
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Santa Clara, CA$148k - $235.8kfull-timePosted 5mo ago

About the role

Senior Photonic Layout Design Engineer responsible for physical design and verification of photonic integrated circuits (PICs), driving designs from concept to manufacturing readiness within a multidisciplinary team focused on Silicon Photonics and SERDES products.

Responsibilities

  • Lead complex, full-loop manual and automated layout designs for waveguides, modulators, photodetectors, and mixed-signal functions (high-speed/general I/Os, ESD structures). Drive full tape-out process, including floor planning, waveguide routing, and mask data preparation.
  • Execute post-layout verification (DRC, LVS, fill, density) across multiple stepping versions.Trace defect sources, mitigate layout-dependent issues, and ensure DRC/LVS cleanliness prior to tape-out.
  • Own the layout of complex test structures, active/passive full loops, and certification vehicles with large DOEs to optimize process windows.
  • Develop and implement AI-assisted design methods, layout automation scripts, and custom Pcells to improve productivity, reduce development cycle times, and customize DRC/LVS checking flows.

Qualifications

  • BS, MS, or Ph.D. in Electrical Engineering, Physics, or closely related field (or equivalent experience)
  • At least 12+ years of hands-on, full-chip layout design experience in semiconductor, analog, or silicon photonics industries
  • Deep understanding of analog circuit layout, Silicon Photonic constraints, and device physics within advanced sub-micron CMOS and SiPh technologies
  • Proven expertise with Cadence Virtuoso (Custom Layout, SDL) and industry-standard verification suites (Calibre, Hercules, ICV, Dracula, or Primeyield)
  • Strong proficiency in programming and scripting languages (Python, SKILL, Perl, TCL, or C++) for layout automation, file I/O, data processing, and tape-out flows
  • Ability to optimize workflows using BKMs and collaborate with integration and design rule teams to achieve high-yield manufacturing goals

Skills

Required:Photonic IC layout designCadence VirtuosoLayout verificationProgramming/scripting for automation

Benefits

  • Eligible for equity and benefits (as described)
Last updated Sep 11, 2026. Interested? Apply on the company site.

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