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Senior Memory Mask Design Engineer

NVIDIA· Engineer, Mask Design
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Bengalurufull-timePosted 5mo ago

About the role

Senior Digital/Memory Mask Design Engineer responsible for high-speed digital memory circuit designs, leading architecture and layout of memory subsystems, and driving physical verification, EM/IR mitigation, and memory compiler development in advanced CMOS nodes.

Responsibilities

  • Implement IC layout of high-performance, high-speed CMOS memory circuits in 3nm, 5nm, 7nm and lower nodes following industry standard methodologies.
  • Lead the architecture and layout design of key memory subsystems including control logic, sense amplifiers, I/O blocks, bit-cell arrays, and decoders for advanced technology nodes.
  • Direct custom layout and verification of complex memory cells, setting standards and methodologies for compiler-driven design flows.
  • Be responsible for and optimize all physical verification activities, including DRC, LVS, density analysis, and comprehensive tape-out checks.
  • Drive identification and resolution of complex physical design issues in compiler-generated layouts, mentoring junior engineers.
  • Provide guidance on IR drop and EM mitigation strategies, establishing design methodologies for robust memory layouts.
  • Possess deep expertise in ultra-deep sub-micron layout challenges, innovating and implementing advanced solutions.
  • Development of memory compilers, leading solving efforts and driving optimization for performance, area, and manufacturability.
  • Cultivate teamwork across multi-functional teams, influencing project direction and ensuring alignment with objectives.
  • Excel in resource management, representing the team in technical discussions with customers.

Qualifications

  • B.E/B Tech in Electronics or M Tech in Electronics or equivalent experience with 6+ years of proven memory layout experience in advanced CMOS process.
  • Detailed knowledge of industry standard EDA tools for Cadence.
  • Experience with layout of high-performance memories of various types.
  • Knowledge of layout basics including bitcells, decoders, LIO, matching devices, symmetrical layout, signal shielding.
  • Experience with floor planning, block-level routing and macro-level assembly.
  • Detailed knowledge of top-level verification including EM/IR quality checks and layout-dependent effects including LOD, dummification, fills.

Skills

Required:Memory layout designEDA tools (Cadence)High-performance memory designFloor planning and routingTop-level verification (EM/IR, LOD, fills)
Last updated Jun 26, 2026. Interested? Apply on the company site.

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