Senior Circuit Methodology Engineer
NVIDIA· Engineer, ASIC Mixed Signal Design
Santa Clara, CA$168k - $264.5kFull-timePosted 5mo ago
About the role
Senior Circuit Methodology Engineer responsible for infrastructure support for circuit design and methodology, owning and evolving compute/GPU infrastructure, and enabling scalable design and verification flows across farm and IT teams.
Responsibilities
- Design, develop, and maintain circuit design and verification flows that run on large-scale compute and GPU farms across geographies via various job schedulers.
- Proactively monitor farm health and job behavior, identify bottlenecks, and implement solutions to improve throughput, utilization, and turnaround time.
- Bring up and release new compute and GPU infrastructure for team use.
- Evaluate and qualify new compute and GPU resources, schedulers, and related EDA infrastructure components.
- Build automation and tooling to streamline flow setup, job submission, resource allocation, logging, and reporting.
- Track measurements (utilization, queue times, failure rates) and lead ongoing improvement projects for farm efficiency and cost effectiveness.
- Provide user support for debug flow, infrastructure, and job-scheduling issues; root-cause failures; and implement permanent fixes.
- Develop and maintain documentation, training materials, and best-practice guidelines for users of the circuit design compute and GPU environment.
- Proactively contribute information to in-house AI systems to provide first-pass user assistance.
Qualifications
- BSEE, BSCE or equivalent experience.
- Mid-level programming skill (primarily Python and Perl).
- 8+ years of experience related to circuit design methodology using Cadence/Synopsys-based systems (Virtuoso/Custom Compiler). Design experience a plus.
- Experience with job schedulers/compute farms, primarily LSF and Slurm.
- Proven ability to debug complex multi-layer issues across flows, scripts, tools, and infrastructure.
- Strong communication skills and ability to partner with diverse engineering teams.
- Exposure to circuit design workloads beneficial.
Skills
Required:PythonPerlCadence VirtuosoCadence/Synopsys toolingLSFSlurm
Benefits
- Eligible for equity and benefits.
Last updated Jun 26, 2026. Interested? Apply on the company site.
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