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Senior Power and Performance Engineer

NVIDIA· Engineer, ASIC
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Santa Clara, CA$168k - $310.5kfull-timePosted 4mo ago

About the role

Silicon Co-design Group (SCG) ArchDev team develops silicon and system-level features, driving power and performance optimization from architecture through bringup and product release.

Responsibilities

  • Architect and integrate system-level performance and power management features, controllers, and policies to optimize product efficiency across datacenter and client products.
  • Build feature roadmaps to address low-power, low-noise, and performance-per-watt needs through prototyping, use-case analysis, and cost/benefit trade-offs.
  • Partner with architecture, ASIC, board/platform, software/firmware, and marketing teams to drive design decisions and debug complex issues.
  • Track industry trends and market needs and translate them into forward-looking roadmaps.
  • Lead debug efforts, develop workarounds, and support bringup, validation, manufacturing, and customer escalations.

Qualifications

  • BS or MS in EE/CE (or equivalent experience) with 8+ years in silicon power architecture, system-level design, validation, and power/performance optimization.
  • Strong EE fundamentals: digital design, low power design, DVFS, control systems, power management, timing, and architecture.
  • Solid understanding of firmware/driver structures and HW/SW interaction.
  • Familiarity with clocking, boot/reset flows, and system architecture is a plus.
  • Hands-on lab experience (oscilloscopes, multimeters, logic analyzers) and silicon bringup exposure are a bonus.
  • Programming proficiency in C/C++, Python, or Perl in Windows/Linux environments.
  • Strong problem-solving, collaboration, and communication skills.

Skills

Required:System-level power and performance optimizationDigital design and low power designFirmware/driver interactionProgramming

Benefits

  • equity
  • benefits package
Last updated Sep 25, 2026. Interested? Apply on the company site.

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